
module Memory (

	input clock,
	input reset,

	// Execute
	input 		[2:0]		ex_mem_msm ,
	input		[2:0]		ex_mem_msl ,
	input					ex_mem_readmem ,
	input					ex_mem_writemem ,
	input					ex_mem_mshw ,
	input					ex_mem_lshw ,
	input		[31:0]		ex_mem_regb ,
	input		[2:0]		ex_mem_selwsource ,
	input		[4:0]		ex_mem_regdest ,
	input					ex_mem_writereg ,
	input		[31:0]		ex_mem_aluout ,
	input		[31:0]		ex_mem_wbvalue ,

	// MC
	output					mem_mc_rw ,
	output					mem_mc_en ,
	output		[31:0]		mem_mc_addr ,
	inout		[31:0]		mem_mc_data ,
	output					mem_mc_en1h ,
	output					mem_mc_en1l ,
	output					mem_mc_en2h ,
	output					mem_mc_en2l ,	

	// Forwarding
	output		[31:0]		mem_fw_wbvalue ,
	output					mem_fw_writereg ,

	// Writeback
	output reg	[4:0]		mem_wb_regdest ,
	output reg				mem_wb_writereg ,
	output reg	[31:0]		mem_wb_wbvalue

	);

	...

endmodule



